`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/06/02 14:46:22
// Design Name: 
// Module Name: seg_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module  seg_tb;
reg   [3:0] bcdnum;
wire   [6:0] seg7;
seg  u1(bcdnum,seg7);
initial  begin
bcdnum=0;
end
always   #10   bcdnum=bcdnum+1;
endmodule
